K.Sandyarani1 and P. Nirmal Kumar2
1Research Scholar, Department of ECE, Sathyabama University, Chennai, India
2Associate Professor, Department of ECE, College of Engineering, Guindy, Anna University, Chennai, India
ABSTRACT
Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm. Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural properties. The AES architecture with the enhanced mix column to be proposed with reduced number of transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding the VLSI design environment. The simulation results of the proposed structure are performed with the minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS technology based AES Algorithm is integrated into the backend based chip technology.
KEYWORDS
Advanced Encryption Standard, Sub-Channel, Mix-Column, Verilog A, Complementary metal oxide semiconductor, Nano-technology.
ORIGINAL SOURCE URL: https://aircconline.com/vlsics/V8N6/8617vlsi02.pdf
http://airccse.org/journal/vlsi/vol8.html
