International Journal of VLSI design & Communication Systems ( VLSICS )
ISSN: 0976 - 1357 (Online); 0976 - 1527(print)
http://airccse.org/journal/vlsi/vlsics.html
Here's where you can reach us: vlsicsjournal@airccse.org or vlsicsjournal@yahoo.com
July 2020: Top Read Articles in VLSI design & Communication Systems
Academia Link
10th International Conference on Digital Image Processing and Pattern Recognition (DPPR 2020)
November 28 ~ 29, 2020, London, United Kingdom
https://cndc2020.org/dppr/index.html
Paper Submission
Authors are invited to submit papers through the conference Submission System by August 15, 2020.
Submission Deadline : August 15, 2020
Contact Us
Here's where you can reach us : dpprc@yahoo.com or dppr@cndc2020.org
T. Suguna and M. Janaki Rani
Department of Electronics and Communication Engineering,
Dr.M.G. R Educational and Research Institute, Chennai, India
ABSTRACT
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.
KEYWORDS
leakage power, low power, voltage scaling, power gating, transistor stacking, adiabatic logic.
Original Source URL:
https://aircconline.com/vlsics/V9N1/9118vlsi01.pdf
http://airccse.org/journal/vlsi/vol9.html
