International Journal Of VLSI Design & Communication Systems ( VLSICS ): June 2020

Friday, 26 June 2020

HARDWARE SECURITY IN CASE OF SCAN-BASED ATTACK ON CRYPTO-HARDWARE

Jayesh Popat and Usha Mehta

EC Department, Nirma University, Gujarat, India

ABSTRACT

The latest innovation technology in computing devices has given a rise of compact, speedy and economical products which also embeds cryptography hardware on-chip. This device generally holds secret key and confidential information, more attention has been given to attacks on hardware which guards such secure information. The attacker may leak secret information from symmetric crypto-hardware (AES, DES etc.) using side-channel analysis, fault injection or exploiting existing test infrastructure. This paper examines various DFT based attack implementation method applied to cryptographic hardware. The paper contains an extensive analysis of attacks based on various parameters. The countermeasures are classified and analyzed in details.

KEYWORDS

Hardware Security, Cryptography, Side-channel analysis, fault injection, scan-based attack, testability, security.

ORIGINAL SOURCE URL : https://aircconline.com/vlsics/V9N2/9218vlsi01.pdf

http://airccse.org/journal/vlsi/vol9.html

Wednesday, 17 June 2020

PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS

PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS

Divya Tripathi and Subodh Wairya

Department of Electronics Engineering, Institute of Engineering & Technology, Lucknow

ABSTRACT

This report examines the subject of sub threshold leakage on carry save adder. When the gate to source voltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit and that is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devices reduces very drastically, and it must be applied in lower power devices since it contributes to low amount of leakage current which confine increases the power consumption of the devices. Adders are the basic building blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficient adders due to its quick and precise computations. Hence this paper performs sub threshold analysis on CSA and the scrutinize results that the total average power is around 4.93µW, the propagation delay for complete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%.

KEYWORDS

Sub threshold Leakage, Gate Diffusion Input (GDI), Carry Save Adder (CSA), Leakage current, Transistor Modeling.

ORIGINAL SOURCE URL : https://aircconline.com/vlsics/V9N3/9318vlsi05.pdf

http://airccse.org/journal/vlsi/vol9.html