VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITS

VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITS

Andrew Suchanek1, Zhong Chen2 and Jia Di1

1Computer Science and Computer Engineering Department, University of Arkansas,Fayetteville, Arkansas, USA

2Electrical Engineering Department, University of Arkansas,Fayetteville, Arkansas, USA

ABSTRACT

Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.

KEYWORDS

Voltage stacking; power management; asynchronous; MTNCL 

Original Source URL : https://aircconline.com/vlsics/V9N4/9418vlsi02.pdf

http://airccse.org/journal/vlsi/vol9.html

International Journal of VLSI design & Communication Systems ( VLSICS )

April 2020: Top Read Articles in VLSI design & Communication Systems!

International Journal of VLSI design & Communication Systems ( VLSICS )
ISSN: 0976 - 1357 (Online); 0976 - 1527(print)
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International Journal of VLSI design & Communication Systems ( VLSICS ) 

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

http://airccse.org/journal/vlsi/vlsics.html

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas. 

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following: 

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

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* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

* Nano Electronics, Molecular, Biological and Quantum Computing

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Important Dates:

• Submission Deadline    : April 18, 2020
• Acceptance Notification : May 18, 2020
• Final Manuscript Due     : May 26, 2020
• Publication Date : Determined by the Editor-in-Chief 

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FIVE-TRANSISTOR SINGLE-PORT SRAM BIT CELL WITH HIGH SPEED AND LOW STANDBY CURRENT

FIVE-TRANSISTOR SINGLE-PORT SRAM BIT CELL WITH HIGH SPEED AND LOW STANDBY CURRENT

Chien-Cheng Yu1,3*, Ming-Chuen Shiau2 , and Ching-Chih Tsai3

1Department of Electronic Engineering, Hsiuping University of Science and Technology,Taichung City, Taiwan

2Department of Electrical Engineering, Hsiuping University of Science and Technology,Taichung City, Taiwan

3Department of Electrical Engineering, National Chung Hsing University,Taichung City, Taiwan

ABSTRACT

In this paper, a new five-transistor (5T) single-port Static Random Access Memory (SRAM) cell with voltage assist is proposed. Amongst them, a word line suppression circuit is designed to provide a voltage of the respective connected word line signal in a selected row cells lower than the power supply voltage VDD by a threshold voltage during a read operation, thereby to improve the read/write-ability of the cell. In addition, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a read operation, a two-stage reading mechanism is engaged to increase the reading speed. Simulation results for the proposed cell design confirm that there is a conspicuous improvement in reading speed and power saving over the conventional SRAM cells, and fast writing also can be achieved.

KEYWORDS

Single-port, Static random access memory, Assist circuitry, Voltage control circuit, Standby start-up circuit

Original Source URL : http://aircconline.com/vlsics/V9N4/9418vlsi01.pdf

http://airccse.org/journal/vlsi/vol9.html