International Journal of VLSI design & Communication Systems( VLSICS )

http://airccse.org/journal/vlsi/vlsics.html

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following:

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

* Post-CMOS VLSI

* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

* Nano Electronics, Molecular, Biological and Quantum Computing

* Intellectual Property Creating and Sharing

* Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through E-mail; vlsicsjournal@airccse.org.  Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates:

·         Submission Deadline    : August 10, 2019

·         Acceptance Notification :September 10, 2019

·         Final Manuscript Due     : September 18, 2019

·         Publication Date : Determined by the Editor-in-Chief

For other details please visit: http://airccse.org/journal/vlsi/vlsics.html

DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATOR

Jayanthi Vanama and G.L.Sampoorna

Trainee Engineer, Powerwave Technologies Pvt. Ltd., R&D India 

Intern, CONEXANT Systems Pvt. Ltd.

ABSTRACT

A low power programmable low drop-out regulator capable of providing 1V output has been proposed. The regulator requires a supply voltage of 1.2V and works in the temperature range of -40 to 125 ˚C in nominal corner (i.e, normal doping for PMOS and NMOS Field Effect Transistors), yielding a load regulation of 3%. The output voltage level is controlled externally by means of 2 1-bit control signals. The circuit provides a DC gain of 30 dB and a maximum DC Power Supply Rejection Ratio of -35 dB and a worst case PSRR of -20 dB. Power dissipation in the load is nearly 100 µW.

KEYWORDS

Low Drop-Out, Voltage Regulator, Low Power, Low quiescent current.

Orginal Sourcr URL: http://aircconline.com/vlsics/V4N3/4313vlsics09.pdf

http://airccse.org/journal/vlsi/vol4.html

A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SLEW RATE 

Sadhana Sharma¹ , Abhay Vidyarthi² and Shyam Akashe³

¹Research Scholar of ITM University, Gwalior, India ²Associate Professor, Dept. of ECE, ITM University, Gwalior, India ³Associate Professor, Dept. of ECE, ITM University, Gwalior, India

ABSTRACT

A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at 45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit is performed with extremely low leakage current as well as high current driving capability for the large input voltages. The proposed paper is achieved very high speed with very low propagation delay range i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by 24% (in ns) at 3V square wave input. The measured quiescent current is 41µA.

KEYWORDS

CMOS buffer, Class-AB, Rail-to-rail, Quiescent current, Lector technique.

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics08.pdf

http://airccse.org/journal/vlsi/vol4.html

5th International Conference on VLSI and Applications (VLSIA-2019)

November 30 ~ December 01, 2019, Dubai, UAE

https://csty2019.org/vlsia/index.html

Call for Papers

5^th International Conference on VLSI and Applications (VLSIA-2019) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of VLSI. Original, unpublished papers, describing research in the general area of VLSI are solicited. Both theoretical and experimental research results are welcome in the following areas, but are not limited to

Topics of interest include, but are not limited to, the following 

·         VLSI Design

·         VLSI Circuits

·         Computer-Aided Design (CAD)

·         Low Power and Power Aware Design

·         Emerging Technologies

·         Post-CMOS VLSI

·         VLSI Applications (communications, video, security, sensor networks, etc.,)

·         Nano Scale Electronic Design and Applications

Paper Submission

Authors are invited to submit papers through the conference Submission System by July 28, 2019. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by Computer Science Conference Proceedings in Computer Science & Information Technology (CS & IT) series (Confirmed).

Selected papers from VLSIA-2019, after further revisions, will be published in the special issue of the following journal.

• International Journal of VLSI Design & Communication Systems (VLSICS)
• Signal & Image Processing : An International Journal (SIPIJ)

Important Dates

·         Submission Deadline : July 28, 2019

·         Authors Notification : August 30, 2019

·         Registration & camera - Ready Paper Due : September 08, 2019

Contact Us

Here's where you can reach us: vlsia@csty2019.org (or) vlsiaconf@yahoo.com

For more details, please visit: https://csty2019.org/vlsia/index.html

Paper Submission Link: https://csty2019.org/submission/index.php

DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGA

Ramneet Kaur¹ and Balwinder Singh²

^1,2Academic and Consultancy Services-Division, Centre for Development of Advanced Computing(C-DAC), Mohali, India

ABSTRACT

As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system has two main modules i.e. identification module and slot checking module. Identification module identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor interfacing, stepper motor and LCD.

KEYWORDS

Finite State Machine; Parking System; Virtex- 5;

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics07.pdf

http://airccse.org/journal/vlsi/vol4.html

CROSSTALK MINIMIZATION FOR COUPLED RLC INTERCONNECTS USING BIDIRECTIONAL BUFFER AND SHIELD INSERTION

Damanpreet Kaur and V.Sulochana

Centre for Development of Advanced Computing (C-DAC) Mohali, India

ABSTRACT

Crosstalk noise is often induced in long interconnects running parallel to each other. There is a need to minimize the effect of these crosstalk noise so as to maintain the signal integrity in interconnects. In this paper crosstalk noise is minimized using various techniques such as repeater (bidirectional buffer) insertion along with shielding, skewing and shielding & skewing simultaneously. With the help of these techniques crosstalk noise is controlled to a great extent in long interconnects. Pre-layout and Post-layout simulations for crosstalk are carried out for these techniques at 180nm technology node using Cadence EDA tools. The influences of these techniques are analyzed and it is found that crosstalk is reduced up to 32 % with repeater insertion, 47% with skewing, 58% with shielding and 81% with skewing & shielding simultaneously.

 KEYWORDS

Crosstalk, Bidirectional Buffer, Shielding, Skewing.

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics04.pdf

http://airccse.org/journal/vlsi/vol4.html