SYNTHESIS OPTIMIZATION FOR FINITE STATE MACHINE DESIGN IN FPGAS

SYNTHESIS OPTIMIZATION FOR FINITE STATE MACHINE DESIGN IN FPGAS

R.UMA AND P. DHAVACHELVAN

Department of Computer Engineering, School of Engineering, Pondicherry University, Pondicherry, India

ABSTRACT

Synthesis optimization plays a vital role in modern FPGAs in order to achieve high performance, in terms of resource utilization and reducing time consuming test process. Cell-based design techniques, such as standard-cells and FPGAs, together with versatile hardware synthesis are rudiments for a high productivity in ASIC  design. As the capacity of FPGAs increases, synthesis tools and efficient synthesis methods for targeted device become more significant to efficiently exploit the  resources and logic capacity. The synthesis tool provides the selection of different constraint to optimize the circuit. This paper presents the design and synthesis  optimization constraints in FPGA for Finite state machine. The primary goal of this sequential logic design is to optimize the speed and area by choosing the proper  options available in the synthesis tool. More over the work focuses the design of FSM with more processes operates at a faster rate and the number of slices utilized  in an FPGA is also reduced when compare to single process. The module functionality are described using Verilog HDL and performance issues like slice utilized,  simulation time, percentage of logic utilization, level of logic are analyzed at 90 nm process technology using SPARTAN6 XC6SLX150 XILINX ISE12.1 tool. 

KEYWORDS

FPGA, FSM optimization, Synthesis constraints, State encoding, logic optimization 

Original Source Link : http://aircconline.com/vlsics/V3N6/3612vlsics07.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN OF REVERSIBLE MULTIPLIERS FOR LINEAR FILTERING APPLICATIONS IN DSP

DESIGN OF REVERSIBLE MULTIPLIERS FOR LINEAR FILTERING APPLICATIONS IN DSP

Rakshith Saligram1  and Rakshith T.R2

1Department of Electronics and Communication, B.M.S College of Engineering, Bangalore, India

2Department of Telecommunication, R. V College of Engineering, Bangalore, India

ABSTRACT

Multipliers in DSP computations are crucial. Thus modern DSP systems need to develop low power multipliers to reduce the power dissipation. One of the efficient ways to reduce power dissipation is by the use of bypassing technique. If a bit in the multiplier and/or multiplicand is zero the whole array of row and/or diagonal will be bypassed and hence the name bypass multipliers. This paper presents the column Bypass multiplier and 2-D bypass multiplier using reversible logic; Reversible logic is a more prominent technology, having its applications in Low Power CMOS and quantum computations. The switching activity of any component in the bypass multiplier depends only on the input bit coefficients. These multipliers find application in linear filtering FFT computational units, particularly during zero padding where there will be umpteen numbers of zeros. A bypass multiplier reduces the number of switching activities as well as the power consumption, above which reversible logic design acts to further almost nullify the dissipations.

KEYWORDS

Reversible logic, Low power Multipliers, Column Bypass multiplier, 2-D Bypass Multiplier ,Reduced Switching Activity, Fast Fourier Transform, Zero Padding. 

Original Source Link : http://aircconline.com/vlsics/V3N6/3612vlsics06.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN AND VLSIIMPLEMENTATION OF ANTICOLLISION ENABLED ROBOT PROCESSOR USING RFID TECHNOLOGY

DESIGN AND VLSIIMPLEMENTATION OF ANTICOLLISION ENABLED ROBOT PROCESSOR USING RFID TECHNOLOGY

Joyashree Bag, Rajanna K M and Subir Kumar Sarkar

Dept. Of Electronics and Telecommunication Engg, Jadavpur University, Kolkata

ABSTRACT

RFID is a low power wireless emerging technology which has given rise to highly promising applications in real life. It can be employed for robot navigation. In multi-robot environment, when many robots are moving in the same workspace, there is a possibility of their physical collision with themselves as well as with physical objects. In the present work, we have proposed and developed a processor incorporating smart algorithm for avoiding such collisions with the help of RFID technology and implemented it by using VHDL. The design procedure and the simulated results are very useful in designing and implementing a practical RFID system. The RTL schematic view of the processor is achieved by successfully synthesizing the proposed design.

KEYWORDS

Navigation, RFID, RTL schematic, Simulation, Synthesis, VHDL 

Original Source Link : http://aircconline.com/vlsics/V3N6/3612vlsics05.pdf

http://airccse.org/journal/vlsi/vol3.html

PERFORMANCE EVALUATION OF THROUGHPUT MAXIMIZATION TECHNIQUE IN MC-CDMA FOR 4G STANDARD

PERFORMANCE EVALUATION OF THROUGHPUT MAXIMIZATION TECHNIQUE IN MC-CDMA FOR 4G STANDARD

Hema Kale1 C.G. Dethe2 and M.M. Mushrif3

1ETC Department , Jhulelal Institute of Technology Nagpur , India.

2ECE Department, Priyadarshni Institute of Engineering and Technology,Nagpur, India.

3ETC Department, Yashwantrao Chavan College of Engineering, Nagpur, India

ABSTRACT

Efficient resource allocation is the major issue in the development of fourth generation mobile communication systems. A very high data rate is needed for advanced multimedia applications and internet. This paper evaluates the performance of improved algorithm for the future Long Term Evolution (LTE) advanced standards-the 3GPP candidate for 4G. For the analysis autoregressive model of correlated Rayleigh fading processes is used. Simulation results shows that for downlink transmission a

very high data rate ,upto hundreds of Mbps can be obtained using improved algorithm under the constraints of available transmit power and given BER. Same algorithm is also analysed by varying the no. of users and spreading factor. Performance of the improved algorithm is evaluated in comparison with ACA algorithm and shows significant improvement in the throughput for the three combining schemes.

KEYWORDS

LTE, MC-CDMA, Autoregressive model , SNR, BER, ACA,CSI.

Original Source Link : http://aircconline.com/vlsics/V3N6/3612vlsics04.pdf

http://airccse.org/journal/vlsi/vol3.html

OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATES

OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATES

H R Bhagyalakshmi1 and M K Venkatesha2

1Department of Electronics and Communication Engineering, B M S College of Engineering, Visvesvaraya Technological University, Bangalore, Karnataka

2Department of Electronics and Communication Engineering, R N S Institute of Technology, Visvesvaraya Technological University, Bangalore, Karnataka

ABSTRACT

Reversible logic is an important area to carry the computation into the world of quantum computing. In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented. BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained. This reduces the total cost of the circuit. Toffoli gate is the universal and also most flexible reversible logic gate. So we have used the Toffoli gates to construct the designed multiplier.

KEYWORDS

Reversible logic gates, Toffoli gates, partial products, multiplier, quantum computing, Nanotechnology, Future computing. 

Original Source Link : http://aircconline.com/vlsics/V3N6/3612vlsics03.pdf

http://airccse.org/journal/vlsi/vol3.html

Feb - International Journal of VLSI design